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ltc2439-1 1 24391f 8-/16-channel 16-bit no latency ds tm adc features applicatio s u typical applicatio u the ltc ? 2439-1 is a 16-channel (8-differential) micropower 16-bit ds analog-to-digital converter. it op- erates from 2.7v to 5.5v and includes an integrated oscillator, 0.12lsb inl and 1 m v rms noise. it uses delta- sigma technology and provides single cycle settling time for multiplexed applications. through a single pin, the ltc2439-1 can be configured for better than 87db differ- ential mode rejection at 50hz and 60hz 2%, or it can be driven by an external oscillator for a user-defined rejec- tion frequency. the internal oscillator requires no external frequency setting components. the ltc2439-1 accepts any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement applications. it can be configured to take 8 differential channels or 16 single-ended channels. the full-scale bipolar input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set between gnd and v cc . the dc common mode input rejection is better than 140db. the ltc2439-1 communicates through a flexible 4-wire digital interface that is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain gauge transducers n instrumentation n data acquisition n industrial process control , ltc and lt are registered trademarks of linear technology corporation. n 16-channel single-ended or 8-channel differential inputs n low supply current (200 m a, 4 m a in autosleep) n rail-to-rail differential input/reference n 16-bit no missing codes n 1 m v rms noise, 16-enobs independent of v ref n very low transition noise: less than 0.02lsb n operates with a reference as low as 100mv with 1.5 m v lsb step size n guaranteed modulator stability and lock-up immunity for any input and reference conditions n single supply 2.7v to 5.5v operation n internal oscillatorno external components required n 87db min, 50hz and 60hz simultaneous notch filter n pin compatible with the 24-bit ltc2418 n 28-lead ssop package no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. minimum resolvable signal vs v ref sdi sck sdo cs f o ref + v cc 9 11 2.7v to 5.5v 20 18 17 16 19 1 f com ref gnd 10 thermocouple 12 15 differential 16-bit ? s adc + 241418 ta01a 4-wire spi interface ltc2439-1 = external oscillator = 50hz and 60hz rejection ch0 ch1 21 22 ch7 ch8 28 1 ch15 8 16-channel mux v ref (v) 0 *for v ref = 0.4v resolution is limited by step size 0 minimum resolvable signal ( v) 10 30 40 50 2 4 5 90 24361 ta02 20 13 60 70 80 descriptio u
ltc2439-1 2 24391f (notes 1, 2) supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2439-1c ............................................ 0 c to 70 c ltc2439-1i ........................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w order part number LTC2439-1CGN ltc2439-1ign t jmax = 125 c, q ja = 110 c/w consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 v cc com ref + ref nc nc ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sdi f o sck sdo cs gnd parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 16 bits integral nonlinearity 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 0.06 lsb 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) l 0.12 1.25 lsb ref + = 2.5v, ref C = gnd, v incm = 1.25v, (notes 6, 15) 0.30 lsb offset error 2.5v ref + v cc , ref C = gnd, l 520 m v gnd in + = in C v cc , (notes 12,15) offset error drift 2.5v ref + v cc , ref C = gnd, 10 nv/ c gnd in + = in C v cc positive full-scale error 2.5v ref + v cc , ref C = gnd, l 0.16 1.25 lsb in + = 0.75ref + , in C = 0.25 ? ref + (note 15) positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error 2.5v ref + v cc , ref C = gnd, l 0.16 1.25 lsb in + = 0.25 ? ref + , in C = 0.75 ? ref + (note 15) negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 0.20 lsb 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 0.20 lsb ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 0.25 lsb output noise 5v v cc 5.5v, ref + = 5v, v ref C = gnd, 1 m v rms gnd in C = in + 5v (note 12) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) electrical characteristics ltc2439-1 3 24391f parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + v cc (note 5) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 49hz to 61.2hz gnd in C = in + v cc , (note 5) input normal mode rejection (note 5) l 87 db 49hz to 61.2hz reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd (note 5) power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 120 db power supply rejection, ref + = 2.5v, ref C = gnd, in C = in + = gnd 120 db simultaneous 50hz/60hz 2% the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co verter characteristics u symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3 v cc + 0.3 v in C absolute/common mode in C voltage l gnd C 0.3 v cc + 0.3 v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1 v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 18 pf c s (in C )in C sampling capacitance 18 pf c s (ref + )ref + sampling capacitance 18 pf c s (ref C )ref C sampling capacitance 18 pf i dc_leak (in + )in + dc leakage current cs = v cc = 5.5v, in + = gnd l C100 1 100 na i dc_leak (in C )in C dc leakage current cs = v cc = 5.5v, in C = 5v l C100 1 100 na i dc_leak (ref + )ref + dc leakage current cs = v cc = 5.5v, ref + = 5v l C100 1 100 na i dc_leak (ref C )ref C dc leakage current cs = v cc = 5.5v, ref C = gnd l C100 1 100 na off channel to on channel isolation dc 140 db (r in = 100 w ) 1hz 140 db f s = 15,3600hz 140 db t open mux break-before-make interval 2.7v v cc 5.5v 100 ns i s(off) channel off leakage current channel at v cc and gnd l C100 1 100 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a d refere ce u u u u ltc2439-1 4 24391f symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o , sdi 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o , sdi 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 8) l 2.5 v sck 2.7v v cc 3.3v (note 8) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 8) l 0.8 v sck 2.7v v cc 5.5v (note 8) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o , sdi i in digital input current 0v v in v cc (note 8) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o , sdi c in digital input capacitance (note 8) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5 v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C 800 m a (note 9) l v cc C 0.5 v sck v ol low level output voltage i o = 1.6ma (note 9) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs u u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 11) l 200 300 m a sleep mode cs = v cc (note 11) l 415 m a sleep mode cs = v cc , 2.7v v cc 3.3v (note 11, 14) 2 m a power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ltc2439-1 5 24391f symbol parameter conditions min typ max units f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time f o = 0v l 143.8 146.7 149.6 ms external oscillator (note 10) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 9) 17.5 khz external oscillator (notes 9, 10) f eosc /8 khz d isck internal sck duty cycle (note 9) l 45 55 % f esck external sck frequency range (note 8) l 2000 khz t lesck external sck low period (note 8) l 250 ns t hesck external sck high period (note 8) l 250 ns t dout_isck internal sck 19-bit data output time internal oscillator (notes 9, 11) l 1.06 1.09 1.11 ms external oscillator (notes 9, 10) l 152/f eosc (in khz) ms t dout_esck external sck 19-bit data output time (note 7) l 19/f esck (in khz) ms t 1 cs to sdo low l 0 200 ns t2 cs - to sdo high z l 0 200 ns t3 cs to sck (note 9) l 0 200 ns t4 cs to sck - (note 8) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns t 7 sdi setup before sck - (note 5) l 100 ns t 8 sdi hold after sck - (note 5) l 100 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics u w note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2, in + and in C are defined as the selected positive and negative input respectively. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. maximum specifications are limited by the lsb step size (v ref /2 16 ) and the single shot measurement. typical specifications are measured from the center of the quantization band. note 7: f o = gnd (internal oscillator) or f eosc = 139800hz 2% (external oscillator). note 8: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 12: 1 m v rms noise is independent of v ref . since the noise performance is limited by the quantization, lowering v ref improves the effective resolution. note 13: guaranteed by design and test correlation. note 14: the low sleep mode current is valid only when cs is high. note 15: these parameters are guaranteed by design over the full supply and temperature range. automated testing proceedures are limited by the lsb step size (v ref /2 16 ). ltc2439-1 6 24391f ch0 to ch15 (pin 21 to pin 28 and pin 1 to pin 8): analog inputs. may be programmed for single-ended or differen- tial mode. v cc (pin 9): positive supply voltage. bypass to gnd (pin 15) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. com (pin 10): the common negative input (in C ) for all single-ended multiplexer configurations. the voltage on channel 0 to 15 and com input pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C 0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique overrange and underrange output codes. ref + (pin 11), ref C (pin 12): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the positive reference input, ref + , is maintained more positive than the negative reference input, ref C , by at least 0.1v. gnd (pin 15): ground. connect this pin to a ground plane through a low impedance connection. cs (pin 16): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 17): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 18): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as the digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 19): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to gnd (f o = 0v), the converter uses its internal oscillator and rejects 50hz and 60hz simultaneously. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter has 87db minimum rejection in the range f eosc /2560 14% and 110db minimum rejection at f eosc /2560 4%. sdi (pin 20): serial digital data input. during the data output period, this pin is used to shift in the multiplexer address started from the first rising sck edge. during the conversion and sleep periods, this pin is in the dont care state. however, a high or low logic level should be maintained on sdi in the dont care mode to avoid an excessive current in the sdi input buffers. nc (pins 13, 14): not internally connected. do not con- nect or connect to ground. uu u pi fu ctio s ltc2439-1 7 24391f figure 1 uu w fu ctio al block diagra test circuits autocalibration and control differential 3rd order ? s modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ch15 com in + in mux sdo sck ref + ref cs sdi f o (int/ext) 24391 f01 + 1.69k sdo 241418 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 241418 ta03 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc converter operation converter operation cycle the ltc2439-1 is a multichannel, low power, delta-sigma analog-to-digital converter with an easy-to-use 4-wire se- rial interface (see figure 1). its operation is made up of three states. the converter operating cycle begins with the con- version, followed by the low power sleep state and ends with the data input/output (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data output (sdo), serial clock (sck) and chip select (cs). initially, the ltc2439-1 performs a conversion. once the conversion is complete, the device enters the sleep state. the part remains in the sleep state as long as cs is high. while in the sleep state, power consumption is reduced by nearly two orders of magnitude. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. applicatio s i for atio wu uu figure 2. ltc2439-1 state transition diagram convert power up in + = ch0, in = ch1 sleep data output address input 24391 f02 true false cs = low and sck ltc2439-1 8 24391f once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high before the first rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the first rising edge of sck, the device begins outputting the conversion result and inputting channel selection bits. taking cs high at this point will terminate the data output state and start a new conversion. the channel selection control bits are shifted in through sdi from the first rising edge of sck and depending on the control bits, the converter updates its channel selection immediately and is valid for the next conversion. the details of channel selection control bits are described in the input data mode section. the output data is shifted out the sdo pin under the control of the serial clock (sck). the output data is updated on the falling edge of sck allowing applicatio s i for atio wu uu cs sdo hi-z sig (0) bit16 msb b22 converson result bit15 bit14 bit13 bit12 bit11 bit6 bit5 bit3 bit2 bit1 lsb bit0 bit4 bit17 sck sdi sleep data input/output bit18 eoc (1) (0) en sgl a2 a1 a0 don? care conversion 24391 f03a odd/ sign conversion result n ?1 address n address n + 1 address n + 2 output n ?1 output n output n + 1 sdo sck sdi operation hi-z don? care conversion n 24391 f03b conversion n + 1 don? care hi-z hi-z conversion result n conversion result n + 1 figure 3b. typical operation sequence the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 19 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. in order to maintain compatibility with 24-/32-bit data transfers, it is possible to clock the ltc2439-1 with additional serial clock pulses. this results in additional data bits which are always logic high. through timing control of the cs and sck pins, the ltc2439-1 offers several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. figure 3a. input/output data timing ltc2439-1 9 24391f conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz and 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2439-1 incorporates a highly accu- rate on-chip oscillator. this eliminates the need for exter- nal frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2436-1 achieves a minimum of 87db rejection over the range 49hz to 61.2hz. ease of use the ltc2439-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2439-1 performs offset and full-scale calibrations in every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2439-1 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion. (see the 3-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a typical duration of 1ms. the por signal clears all internal registers. following the por signal, the ltc2439-1 starts a normal conversion cycle and follows the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range the ltc2439-1 accepts a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2439-1 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is deter- mined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will significantly improve the converters effective resolution, since the thermal noise (1 m v) is well below the quantiza- tion level of the device (75.6 m v for a 5v reference). at the minimum reference (100mv) the thermal noise remains constant at 1 m v rms (or 6 m v p-p ), while the quantization is reduced to 1.5 m v per lsb. as a result, lowering the reference improves the effective resolution for low level input voltages. input voltage range the two selected pins are labeled in + and in C (see table 1). once selected (either differential or single-ended multiplex- ing mode), the analog input is differential with a common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2439-1 converts the bipolar differential input sig- nal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range the converter indicates the overrange or the underrange con- dition using distinct output codes. input signals applied to in + and in C pins may extend 300mv below ground or above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + or in C pins without affecting the performance of the device. in the physical layout, it is important to applicatio s i for atio wu uu ltc2439-1 10 24391f table 1. channel selection mux address channel selection odd/ sgl sign a2 a1 a0 0 123456789101112131415com *00000in + in C 00001 in + in C 00010 in + in C 00011 in + in C 00100 in + in C 00101 in + in C 00110 in + in C 00111 in + in C 01000in C in + 01001 in C in + 01010 in C in + 01011 in C in + 01100 in C in + 01101 in C in + 01110 in C in + 01111 in C in + 10000in + in C 10001 in + in C 10010 in + in C 10011 in + in C 10100 in + in C 10101 in + in C 10110 in + in C 10111 in + in C 11000 in + in C 11001 in + in C 11010 in + in C 11011 in + in C 11100 in + in C 11101 in + in C 11110 in + in C 11111 in + in C *default at power up applicatio s i for atio wu uu maintain the parasitic capacitance of the connection be- tween these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 10na input leakage current will develop a 1lbs offset error on an 8k resistor if v ref = 5v. this error has a very strong tempera- ture dependency. ltc2439-1 11 24391f input data format when the ltc2439-1 is powered up, the default selection used for the first conversion is in + = ch0 and in C = ch1 (address = 00000). in the data input/output mode follow- ing the first conversion, a channel selection can be up- dated using an 8-bit word. the ltc2439-1 serial input data is clocked into the sdi pin on the rising edge of sck (see figure 3a). the input is composed of an 8-bit word with the first 3 bits acting as control bits and the remaining 5 bits as the channel address bits. the first 2 bits are always 10 for proper updating opera- tion. the third bit is en. for en = 1, the following 5 bits are used to update the input channel selection. for en = 0, previous channel selection is kept and the following bits are ignored. therefore, the address is updated when the 3 control bits are 101 and kept for 100. alternatively, the 3 control bits can be all zero to keep the previous address. this alternation is intended to simplify the sdi interface allowing the user to simply connect sdi to ground if no update is needed. combinations other than 101, 100 and 000 of the 3 control bits should be avoided. when update operation is set (101), the following 5 bits are the channel address. the first bit, sgl, decides if the differential selection mode (sgl = 0) or the single-ended selection mode is used (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input; for sgl = 1, one of the 16 channels (ch0-ch15) is selected as the positive input and the com pin is used as the negative input. for a given channel selection, the converter will measure the voltage between the two chan- nels indicated by in + and in C in the selected row of table 1. output data format the ltc2439-1 serial output data stream is 19 bits long. the first 3 bits represent status information indicating the conversion state and sign. the next 16 bits are the conver- sion result, msb first. the third and fourth bit together are also used to indicate an underrange condition (both bits low means the differential input voltage is below Cfs) or an overrange condition (both bits high means the differential input voltage is above +fs). bit 18 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 17 (second output bit) is a dummy bit (dmy) and is always low. bit 16 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 15 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 16 also provides the underrange or overrange indication. if both bit 16 and bit 15 are high, the differential input voltage is above +fs. if both bit 16 and bit 15 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 2. table 2. ltc2439-1 status bits bit 18 bit 17 bit 16 bit 15 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 15-0 are the 16-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3a. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external micro- controller. bit 18 (eoc) can be captured on the first rising edge of sck. bit 17 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 18th sck and may be latched on the rising edge of the 19th sck pulse. on the falling edge of the 19th sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc applicatio s i for atio wu uu ltc2439-1 12 24391f (bit 18) for the next conversion cycle. table 3 summarizes the output data format. in order to remain compatible with some spi microcontrollers, more than 19 sck clock pulses may be applied. as long as these clock pulses are complete before the conversion ends, they will not effect the serial data. however, switching sck during a conversion may gener- ate ground currents in the device leading to extra offset and noise error sources. as long as the voltage applied to any channel (ch0-ch15, com) is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C 0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differ- ential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. simultaneous frequency rejection the ltc2439-1 internal oscillator provides better than 87db normal mode rejection over the range of 49hz to 61.2hz as shown in figure 4. for simultaneous 50hz/60hz rejection using the internal oscillator, f o should be con- nected to gnd. when a fundamental rejection frequency different from the range 49hz to 61.2hz is required or when the converter must be sychronized with an outside source, the ltc2439-1 applicatio s i for atio wu uu can operate with an external conversion clock. the conveter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, t heo and t leo , are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2439-1 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4%. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 5. whenever an external clock is not present at the f o pin the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2439-1 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the con- verter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 4 summarizes the duration of each state and the achievable output data rate as a function of f o . figure 4. ltc2439-1 normal mode rejection when using an internal oscillator 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 24391 f04a ?0 ?0 100 100 120 130 140 figure 5. ltc2439-1 normal mode rejection when using an external oscillator of frequency f eosc differential input signal frequency deviation from notch frequency f eosc /2560(%) 12 8 404812 normal mode rejection (db) 24361 f04b ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 ltc2439-1 13 24391f applicatio s i for atio wu uu table 3. ltc2439-1 output data format differential input voltage bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 0 v in * eoc dmy sig msb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . table 4. ltc2439-1 state duration state operating mode duration convert internal oscillator f o = low 147ms, output data rate 6.8 readings/s simultaneous 50hz/60hz rejection external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low as long as cs = low but not longer than 1.09ms (internal oscillator) (19 sck cycles) f o = external oscillator with as long as cs = low but not longer than 152/f eosc ms frequency f eosc khz (19 sck cycles) external serial clock with as long as cs = low but not longer than 19/f sck ms frequency f sck khz (19 sck cycles) in the internal sck mode of operation, the sck pin is an output and the ltc2439-1 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is de- tected at the cs pin. if sck is high or floating at power- up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this tran- sition, the converter enters the external sck mode. serial data input (sdi) the serial data input pin, sdi (pin 20), is used to shift in the channel control bits during the data output state to prepare the channel selection for the following conversion. serial interface pins the ltc2439-1 transmits the conversion results and re- ceives the start of conversion command through a syn- chronous 4-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data i/o state it is used to read the conversion result and write in channel selection bits. serial clock input/output (sck) the serial clock signal present on sck (pin 18) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock and each input bit is shifted in the sdi pin on the rising edge of the serial clock. ltc2439-1 14 24391f finally, cs can be used to control the free-running mode of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . serial interface timing modes the ltc2439-1s 4-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 3- or 4-wire i/o, single cycle conversion. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 6 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 6. the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is complete. if cs is high, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state, its conversion result is held in an internal static shift register. the device remains in the sleep state until the first rising edge of sck table 6. ltc2439-1 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 3-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 11 when cs (pin 16) is high or the converter is in the con- version state, the sdi input is ignored and may be driven high or low. when cs goes low and the conversion is complete, sdo goes low and then sdi starts to shift in bits on the rising edge of sck. serial data output (sdo) the serial data output pin, sdo (pin 17), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 16) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 16), is used to test the conversion status and to enable the data input/output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2439-1 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data input/output state (i.e., after the first rising edge of sck occurs with cs = low). if the device has not finished loading the last input bit (a0 of sdi) by the time cs pulled high, the address information is discarded and the previous ad- dress is kept. applicatio s i for atio wu uu ltc2439-1 15 24391f applicatio s i for atio wu uu figure 6. external serial clock, single cycle operation eoc bit 18 sdo sck (external) cs (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care test eoc lbs msb sig bit 0 bit 6 bit 14 bit 13 bit 12 bit 11 bit 15 bit 16 bit 17 sleep sleep data output conversion 24391 f05 conversion hi-z hi-z hi-z test eoc v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs 1 f 2.7v to 5.5v ltc2439-1 4-wire spi interface don? care test eoc (optional) = external clock source = internal osc/simultaneous 50hz/60hz rejection (0) is seen while cs is low. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck . this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 19th rising edge of sck. on the 19th falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the19th falling edge of sck, see figure 7. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. if the device has not finished loading the last input bit a0 of sdi by the time cs is pulled high, the address information is discarded and the previ- ous address is kept. this is useful for aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 3-wire i/o this timing mode utilizes a 3-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 8. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded typically 1ms after v cc exceeds approximately 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion ends. on the falling edge of eoc, the conversion result is loaded into an internal static ltc2439-1 16 24391f figure 7. external serial clock, reduced data output length (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (external) cs data output conversion sleep sleep sleep test eoc data output hi-z hi-z hi-z conversion 24391 f06 msb sig bit 4 bit 14 bit 13 bit 12 bit 11 bit 5 bit 15 bit 16 bit 17 eoc bit 18 bit 0 eoc hi-z test eoc v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs 1 f 2.7v to 5.5v ltc2439-1 4-wire spi interface test eoc (optional) = external clock source = internal osc/simultaneous 50hz/60hz rejection ? applicatio s i for atio wu uu shift register. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. eoc can be latched on the first rising edge of sck. on the 19th falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. figure 8. external serial clock, cs = 0 operation (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care eoc bit 18 sdo sck (external) cs msb sig bit 0 lsb bit 6 bit 14 bit 13 bit 12 bit 11 bit 15 bit 16 bit 17 data output conversion 24391 f07 conversion v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs 1 f 2.7v to 5.5v ltc2439-1 3-wire spi interface = external clock source = internal osc/simultaneous 50hz/60hz rejection ? ltc2439-1 17 24391f applicatio s i for atio wu uu internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 9. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is complete. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the low power mode during the eoc test. in order to allow the device to return to the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f o = logic low or high). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device returns to the sleep state and the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data i/o cycle concludes after the 19th rising edge. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 19th rising edge of sck. after the 19th rising edge, sdo goes high (eoc = 1), sck stays high and a new conversion starts. figure 9. internal serial clock, single cycle operation (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (internal) cs msb sig bit 0 lsb bit 6 test eoc bit 14 bit 13 bit 12 bit 11 bit 15 bit 16 bit 17 eoc bit 18 sleep sleep data output conversion conversion 24391 f08 |